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r10ds0090ej0400 rev.4.00 page 1 of 38 nov 09, 2012 datasheet pd46365084b pd46365094b pd46365184b pd46365364b 36m-bit qdr tm ii sram 4-word burst operation description the pd46365084b is a 4,194,304-word by 8-bit, the pd46365094b is a 4,194,304-word by 9-bit, the pd46365184b is a 2,097,152-word by 18-bit and the pd46365364b is a 1,048,576-word by 36-bit synchronous quad data rate static ram fabricated with advanced cmos technology using full cmos six- transistor memory cell. the pd46365084b, pd46365094b, pd46365184b and pd46365364b integrate unique synchronous peripheral circuitry and a burst counter. all input regist ers controlled by an input clock pair (k and k#) are latched on the positive edge of k and k#. these prod ucts are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic bga. features ? 1.8 0.1 v power supply ? 165-pin plastic bga (13 x 15) ? hstl interface ? pll circuitry for wide output data va lid window and future frequency scaling ? separate independent read and write da ta ports with concurrent transactions ? 100% bus utilization ddr read and write operation ? four-tick burst for reduced address frequency ? two input clocks (k and k#) for precise ddr timing at clock rising edges only ? two output clocks (c and c#) for precise flight time and clock skew matching-clock and da ta delivered together to receiving device ? internally self-timed write control ? clock-stop capability. normal operation is restored in 20 s after clock is resumed. ? user programmable impedance output (35 to 70 ) ? fast clock cycle time : 3.3 ns (300 mhz) , 4.0 ns (250 mhz) ? simple control logic for easy depth expansion ? jtag 1149.1 compatible test access port r10ds0090ej0400 rev.4.00 nov 09 2012
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 2 of 38 nov 09, 2012 ordering information part no. organization (word x bit) cycle time clock frequency core supply voltage operating ambient temperature package pd46365084bf1-e33-eq1-a 4m x 8 3.3ns 300mhz 1.8 0.1 v t a = 0 to 70c 165-pin PD46365084BF1-E40-EQ1-a 4.0ns 250mhz plastic pd46365094bf1-e33-eq1-a 4m x 9 3.3ns 300mhz bga pd46365094bf1-e40-eq1-a 4.0ns 250mhz (13 x 15) pd46365184bf1-e33-eq1-a 2m x 18 3.3ns 300mhz lead-free pd46365184bf1-e40-eq1-a 4.0ns 250mhz pd46365364bf1-e33-eq1-a 1m x 36 3.3ns 300mhz pd46365364bf1-e40-eq1-a 4.0ns 250mhz pd46365084bf1-e33y-eq1-a 4m x 8 3.3ns 300mhz 1.8 0.1 v t a = ? 40 to 85c pd46365084bf1-e40y-eq1-a 4.0ns 250mhz pd46365094bf1-e33y-eq1-a 4m x 9 3.3ns 300mhz pd46365094bf1-e40y-eq1-a 4.0ns 250mhz pd46365184bf1-e33y-eq1-a 2m x 18 3.3ns 300mhz pd46365184bf1-e40y-eq1-a 4.0ns 250mhz pd46365364bf1-e33y-eq1-a 1m x 36 3.3ns 300mhz pd46365364bf1-e40y-eq1-a 4.0ns 250mhz pd46365084bf1-e33-eq1 4m x 8 3.3ns 300mhz 1.8 0.1 v t a = 0 to 70c 165-pin PD46365084BF1-E40-EQ1 4.0ns 250mhz plastic pd46365094bf1-e33-eq1 4m x 9 3.3ns 300mhz bga pd46365094bf1-e40-eq1 4.0ns 250mhz (13 x 15) pd46365184bf1-e33-eq1 2m x 18 3.3ns 300mhz lead pd46365184bf1-e40-eq1 4.0ns 250mhz pd46365364bf1-e33-eq1 1m x 36 3.3ns 300mhz pd46365364bf1-e40-eq1 4.0ns 250mhz pd46365084bf1-e33y-eq1 4m x 8 3.3ns 300mhz 1.8 0.1 v t a = ? 40 to 85c pd46365084bf1-e40y-eq1 4.0ns 250mhz pd46365094bf1-e33y-eq1 4m x 9 3.3ns 300mhz pd46365094bf1-e40y-eq1 4.0ns 250mhz pd46365184bf1-e33y-eq1 2m x 18 3.3ns 300mhz pd46365184bf1-e40y-eq1 4.0ns 250mhz pd46365364bf1-e33y-eq1 1m x 36 3.3ns 300mhz pd46365364bf1-e40y-eq1 4.0ns 250mhz
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 3 of 38 nov 09, 2012 pin arrangement 165-pin plastic bga (13 x 15) (top view) [ pd46365084b] 4m x 8 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss /72m a w# nw1# k# nc/144m r# a a cq b nc nc nc a nc/288m k nw0# a nc nc q3 c nc nc nc v ss a nc a v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v dd q v ss v ss v ss v dd qnc d2 q2 f nc nc nc v dd q v dd v ss v dd v dd q nc nc nc g nc d5 q5 v dd q v dd v ss v dd v dd q nc nc nc h dll# v ref v dd q v dd q v dd v ss v dd v dd qv dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd qnc q1 d1 k nc nc nc v dd q v dd v ss v dd v dd q nc nc nc l nc q6 d6 v dd q v ss v ss v ss v dd qnc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss a a a v ss nc nc nc p nc nc q7 a a c a a nc nc nc r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d7 : data inputs tdi : ieee 1149.1 test input q0 to q7 : data outputs tc k : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input nw0#, nw1# : nibble write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching nc/xxm : expansion address for xxmb dll# : pll disable remarks 1. # indicates active low. 2 . refer to package dimensions for the index mark. 3 . 2a, 7a and 5b are expansion addresses : 2a for 72mb : 2a and 7a for 144mb : 2a, 7a and 5b for 288mb. 2a of this product can also be used as nc.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 4 of 38 nov 09, 2012 pin arrangement 165-pin plastic bga (13 x 15) (top view) [ pd46365094b] 4m x 9 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss /72m a w# nc k# nc/144m r# a a cq b nc nc nc a nc/288m k bw0# a nc nc q4 c nc nc nc v ss a nc a v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v dd q v ss v ss v ss v dd qnc d3 q3 f nc nc nc v dd q v dd v ss v dd v dd q nc nc nc g nc d6 q6 v dd q v dd v ss v dd v dd q nc nc nc h dll# v ref v dd q v dd q v dd v ss v dd v dd qv dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd qnc q2 d2 k nc nc nc v dd q v dd v ss v dd v dd q nc nc nc l nc q7 d7 v dd q v ss v ss v ss v dd qnc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss a a a v ss nc nc nc p nc nc q8 a a c a a nc d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d8 : data inputs tdi : ieee 1149.1 test input q0 to q8 : data outputs tc k : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching nc/xxm : expansion address for xxmb dll# : pll disable remarks 1. # indicates active low. 2. refer to package dimensions for the index mark. 3. 2a, 7a and 5b are expansion addresses : 2a for 72mb : 2a and 7a for 144mb : 2a, 7a and 5b for 288mb 2a of this product can also be used as nc.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 5 of 38 nov 09, 2012 pin arrangement 165-pin plastic bga (13 x 15) (top view) [ pd46365184b] 2m x 18 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss /144m a w# bw1# k# nc/288m r# a v ss /72m cq b nc q9 d9 a nc k bw0# a nc nc q8 c nc nc d10 v ss a nc a v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v dd q v ss v ss v ss v dd qnc d6 q6 f nc q12 d12 v dd q v dd v ss v dd v dd qnc nc q5 g nc d13 q13 v dd q v dd v ss v dd v dd q nc nc d5 h dll# v ref v dd q v dd q v dd v ss v dd v dd qv dd q v ref zq j nc nc d14 v dd q v dd v ss v dd v dd qnc q4 d4 k nc nc q14 v dd q v dd v ss v dd v dd qnc d3 q3 l nc q15 d15 v dd q v ss v ss v ss v dd qnc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss a a a v ss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d17 : data inputs tdi : ieee 1149.1 test input q0 to q17 : data outputs tc k : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0#, bw1# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching nc/xxm : expansion address for xxmb dll# : pll disable remarks 1. # indicates active low. 2. refer to package dimensions for the index mark. 3. 2a, 7a and 10a are expansion addresses : 10a for 72mb : 10a and 2a for 144mb : 10a, 2a and 7a for 288mb 2a and 10a of this product can also be used as nc.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 6 of 38 nov 09, 2012 pin arrangement 165-pin plastic bga (13 x 15) (top view) [ pd46365364b] 1m x 36 1 2 3 4 5 6 7 8 9 10 11 a cq# v ss /288m nc/72m w# bw2# k# bw1# r# a v ss /144m cq b q27 q18 d18 a bw3# k bw0# a d17 q17 q8 c d27 q28 d19 v ss a nc a v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v dd q v ss v ss v ss v dd q q15 d6 q6 f q30 q21 d21 v dd q v dd v ss v dd v dd q d14 q14 q5 g d30 d22 q22 v dd q v dd v ss v dd v dd q q13 d13 d5 h dll# v ref v dd q v dd q v dd v ss v dd v dd qv dd q v ref zq j d31 q31 d23 v dd q v dd v ss v dd v dd qd12 q4 d4 k q32 d32 q23 v dd q v dd v ss v dd v dd q q12 d3 q3 l q33 q24 d24 v dd q v ss v ss v ss v dd q d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss a a a v ss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdo tck a a a c# a a a tms tdi a : address inputs tms : ieee 1149.1 test input d0 to d35 : data inputs tdi : ieee 1149.1 test input q0 to q35 : data outputs tc k : ieee 1149.1 clock input r# : read input tdo : ieee 1149.1 test output w# : write input v ref : hstl input reference input bw0# to bw3# : byte write data select v dd : power supply k, k# : input clock v dd q : power supply c, c# : output clock v ss : ground cq, cq# : echo clock nc : no connection zq : output impedance matching nc/xxm : expansion address for xxmb dll# : pll disable remarks 1. # indicates active low. 2. refer to package dimensions for the index mark. 3. 2a, 3a and 10a are expansion addresses : 3a for 72mb : 3a and 10a for 144mb : 3a, 10a and 2a for 288mb 2a and 10a of this product can also be used as nc.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 7 of 38 nov 09, 2012 pin description (1/2) symbol type description a input synchronous address inputs: these inputs ar e registered and must meet the setup and hold times around the rising edge of k. all tr ansactions operate on a burst of four words (two clock periods of bus activity). thes e inputs are ignored when device is deselected, i.e., nop (r# = w# = high). d0 to dxx input synchronous data inputs: input dat a must meet setup and hold times around the rising edges of k and k# during write operations. see pin arrangement for ball site location of individual signals. x8 device uses d0 to d7. x9 device uses d0 to d8. x18 device uses d0 to d17. x36 device uses d0 to d35. q0 to qxx output synchronous data outputs: output data is synchronized to the respective c and c# or to k and k# rising edges if c and c# are tied high. data is output in synchronization with c and c# (or k and k#), depending on the r# command. see pin arrangement for ball site location of individual signals. x8 device uses q0 to q7. x9 device uses q0 to q8. x18 device uses q0 to q17. x36 device uses q0 to q35. r# input synchronous read: when low this input causes the address inputs to be registered and a read cycle to be initiated. this input mu st meet setup and hold times around the rising edge of k. if a read command (r# = low) is input, an input of r# on the subsequent rising edge of k is ignored. w# input synchronous write: when low this input c auses the address inputs to be registered and a write cycle to be initiated. this input mu st meet setup and hold times around the rising edge of k. if a write command (w# = low) is input, an input of w# on the subsequent rising edge of k is ignored. bwx# nwx# input synchronous byte writes (nibble writes on x8): when low these inputs cause their respective byte or nibble to be registered and written during write cycles. these signals must meet setup and hold times around the ri sing edges of k and k# for each of the two rising edges comprising the write cycle. see pin arrangement for signal to data relationships. x8 device uses nw0#, nw1#. x9 device uses bw0#. x18 device uses bw0#, bw1#. x36 device uses bw0# to bw3#. see byte write operation for relation between bwx#, nwx# and dxx. k, k# input input clock: this input clock pair registers ad dress and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchron ous inputs must meet setup and hold times around the clock rising edges. c, c# input output clock: this clock pair provides a us er controlled means of tuning device output data. the rising edge of c# is used as the out put timing reference for first and third output data. the rising edge of c is used as the ou tput reference for second and fourth output data. ideally, c# is 180 degr ees out of phase with c. when use of k and k# as the reference instead of c and c#, then fixed c and c# to high. operation cannot be guaranteed unless c and c# are fixed to high (i.e. toggle of c and c#).
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 8 of 38 nov 09, 2012 (2/2) symbol type description cq, cq# output synchronous echo cl ock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tristates. if c and c# are stopped (if k and k# are stopped in the single clock mode), cq and cq# will also stop. zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q, cq and cq# output impedance are set to 0.2 x rq, where rq is a resistor from this bump to ground. the output impedance can be minimized by directly connect zq to v dd q. this pin cannot be connected directly to gnd or left unconnected. the output imped ance is adjusted every 20 s upon power-up to account for drifts in supply voltage and temperature. after replacement for a resistor, the new output impedance is reset by implementing power-on sequence. dll# input pll disable: when debug ging the system or board, the o peration can be performed at a clock frequency slower than tkhkh (max.) wit hout the pll circuit being used, if dll# = low. the ac/dc characteristics cannot be guaranteed. for normal operation, dll# must be high and it can be connected to v dd q through a 10 k or less resistor. tms tdi input ieee 1149.1 test inputs: 1.8 v i/o level. these balls ma y be left not connected if the jtag function is not used in the circuit. tck input ieee 1149.1 clock input: 1.8 v i/o level. this pin must be tied to v ss if the jtag function is not used in the circuit. tdo output ieee 1149.1 test output: 1.8 v i/o level. when providing any external voltage to tdo signal, it is recommended to pull up to v dd . v ref ? hstl input reference voltage: nominally v dd q /2. provides a reference voltage for the input buffers. v dd supply power supply: 1.8 v nominal. see recommended dc operating conditions and dc characteristics for range. v dd q supply power supply: isolated output buffer supply. nominally 1.5 v. 1.8 v is also permissible. see recommended dc operating conditions and dc characteristics for range. v ss supply power supply: ground nc ? no connect: these signals are not connected internally.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 9 of 38 nov 09, 2012 block diagram [ pd46365084b] [ pd46365094b] data registry & logic output register w# nw0# nw1# r# k k# k k r# w# k address 20 20 d0 to d7 8 output select output buffer 8 16 16 16 32 16 mux mux address registry & logic 2 20 x 32 memory array write driver sense amps write register q0 to q7 c, c# or k, k# cq, cq# 2 data registry & logic output register w# bw0# r# k k# k k r# w# k address 20 20 d0 to d8 9 output select output buffer 9 18 18 18 36 18 mux mux address registry & logic 2 20 x 36 memory array write driver sense amps write register q0 to q8 c, c# or k, k# cq, cq# 2
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 10 of 38 nov 09, 2012 [ pd46365184b] [ pd46365364b] data registry & logic output register w# bw0# bw1# r# k k# k k r# w# k address 19 19 d0 to d17 18 output select output buffer 18 36 36 36 72 36 mux mux address registry & logic 2 19 x 72 memory array write driver sense amps write register q0 to q17 c, c# or k, k# cq, cq# 2 data registry & logic output register w# bw0# bw1# r# k k# k k r# w# k address 18 18 d0 to d35 36 output select output buffer 36 72 72 72 144 72 mux mux address registry & logic 2 18 x 144 memory array write driver sense amps write register q0 to q35 c, c# or k, k# cq, cq# 2 bw2# bw3#
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 11 of 38 nov 09, 2012 power-on sequence in qdr ii sram qdr ii srams must be powered up and initialized in a predefined manner to prevent undefined operations. the following timing charts show the recommended power-on sequence. the following power-up supply voltage application is recommended: v ss , v dd , v dd q, v ref , then v in . v dd and v dd q can be applied simultaneously, as long as v dd q does not exceed v dd by more than 0.5 v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v dd q, v dd , v ss . v dd and v dd q can be removed simultaneously, as long as v dd q does not exceed v dd by more than 0.5 v during power-down. power-on sequence apply power and tie dll# to high. apply v dd q before v ref or at the same time as v ref . provide stable clock for more than 20 s to lock the pll. continuous min.4 nop(r# = high) cycles are required after pll lock up is done. pll constraints the pll uses k clock as its synchronizing input and the in put should have low phase jitter which is specified as tkc var. the pll can cover 120 mhz as the lowest freq uency. if the input clock is unstable and the pll is enabled, then the pll may lock onto an undesired clock frequency. power-on waveforms 20 s or more stable clock v dd /v dd q stable (< 0.1 v dc per 50 ns) v dd /v dd q clock unstable clock normal operation start dll# fix high (or tied to v dd q) r# 4 times nop
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 12 of 38 nov 09, 2012 truth table operation clk r# w# d or q write cycle l h h l data in load address, input write data on input data da(a+0) da(a+1) da(a+2) da(a+3) consecutive k and k# rising edge input clock k(t+1) k#(t+1) k(t+2) k#(t+2) read cycle l h l data out load address, read data on output data qa(a+0) qa(a+1) qa(a+2) qa(a+3) consecutive c and c# rising edge output clock c#(t+1) c(t+2) c#(t+2) c(t+3) nop (no operation) l h h h d = , q = high-z clock stop stopped previous state remarks 1. h : high, l : low, : don?t care, : rising edge. 2. data inputs are registered at k and k# rising edges. data outputs are delivered at c and c# rising edges except if c and c# are high th en data outputs are delivered at k and k# rising edges. 3. all control inputs in the truth table must meet set up/hold times around the rising edge (low to high) of k. all control inputs are registered during the rising edge of k. 4. this device contains circuitry that ensure the outputs to be in high impedance during power-up. 5. refer to state diagram and tim ing diagrams for clarification. 6. it is recommended that k = k# = c = c# when clock is stopped. this is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. if r# was low to initiate the previous cycle, this signal becomes a don't care for this write operation however it is strongly recommended that this signal is brought high as shown in the truth table. 8. w# during write cycle and r# during read cycle we re high on previous k clock rising edge. initiating consecutive read or write operations on consecutive k clock rising edges is not permitted. the device will ignore the second request.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 13 of 38 nov 09, 2012 byte write operation [ pd46365084b] operation k k# nw0# nw1# write d0 to d7 l h ? 0 0 ? l h 0 0 write d0 to d3 l h ? 0 1 ? l h 0 1 write d4 to d7 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. nw0# and nw 1# can be altered for any portion of the burst write operation provided that the setu p and hold requirements are satisfied. [ pd46365094b] operation k k# bw0# write d0 to d8 l h ? 0 ? l h 0 write nothing l h ? 1 ? l h 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. [ pd46365184b] operation k k# bw0# bw1# write d0 to d17 l h ? 0 0 ? l h 0 0 write d0 to d8 l h ? 0 1 ? l h 0 1 write d9 to d17 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# and bw1# can be altered for any portion of the burst write operation provided that the setu p and hold requirements are satisfied.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 14 of 38 nov 09, 2012 [ pd46365364b] operation k k# bw0# bw1# bw2# bw3# write d0 to d35 l h ? 0 0 0 0 ? l h 0 0 0 0 write d0 to d8 l h ? 0 1 1 1 ? l h 0 1 1 1 write d9 to d17 l h ? 1 0 1 1 ? l h 1 0 1 1 write d18 to d26 l h ? 1 1 0 1 ? l h 1 1 0 1 write d27 to d35 l h ? 1 1 1 0 ? l h 1 1 1 0 write nothing l h ? 1 1 1 1 ? l h 1 1 1 1 remarks 1. h : high, l : low, : rising edge. 2. assumes a write cycle was initiated. bw0# to bw 3# can be altered for any portion of the burst write operation provided that the setu p and hold requirements are satisfied.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 15 of 38 nov 09, 2012 bus cycle state diagram read double; r_count = r_count+2 write double; w_count = w_count+2 power up always r# = high supply voltage provided load new read address; r_count = 0; r_init = 1 read port nop r_init = 0 r# = low & r_count = 4 w# = high write port nop load new write address; w_count = 0 always w# = low & w_count = 4 w# = low r_init = 0 r# = low supply voltage provided increment read address by two r_init = 0 increment write address by two w_count = 2 r_count = 2 always always w# = high & w_count = 4 r# = high & r_count = 4 remarks 1. the address is concatenated with two additional internal lsbs to facilitate burst operation. the address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. bus cycle is terminated at the end of this sequence (burst count = 4). 2. read and write state machines can be active simultaneously. read and write cannot be simultaneously initiated. read takes precedence. 3. state machine control timing is controlled by k.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 16 of 38 nov 09, 2012 electrical characteristics absolute maximum ratings parameter symbol conditions rating unit supply voltage v dd ? 0.5 to + 2.5 v output supply voltage v dd q ? 0.5 to v dd v input voltage v in ? 0.5 to v dd + 0.5 (2.5 v max.) v input / output voltage v i/o ? 0.5 to v dd q + 0.5 (2.5 v max.) v operating ambient temperature t a (e** series) 0 to 70 c (e**y series) -40 to 85 c storage temperature t stg ? 55 to + 125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70c, t a = ? 40 to 85c e parameter symbol conditions min. typ. max. unit note supply voltage v dd 1.7 1.8 1.9 v output supply voltage v dd q 1.4 v dd v 1 input high voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v 1, 2 input low voltage v il (dc) ? 0.3 v ref ? 0.1 v 1, 2 clock input voltage v in ? 0.3 v dd q + 0.3 v 1, 2 reference voltage v ref 0.68 0.95 v notes 1. during normal operation, v dd q must not exceed v dd . 2. power-up: vih v dd q + 0.3 v and v dd 1.7 v and v dd q 1.4 v for t 200 ms recommended ac operating conditions (t a = 0 to 70 c, t a = ? 40 to 85c) parameter symbol conditions min. max. unit note input high voltage v ih (ac) v ref + 0.2 v 1 input low voltage v il (ac) v ref ? 0.2 v 1 note 1. overshoot: v ih (ac) v dd + 0.7 v (2.5 v max.) for t tkhkh/2 undershoot: v il (ac) ? 0.5 v for t tkhkh/2 control input signals may not have pulse widths less th an tkhkl (min.) or operate at cycle rates less than tkhkh (min.).
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 17 of 38 nov 09, 2012 dc characteristics 1 (t a = 0 to 70 c, v dd = 1.8 0.1 v) parameter symbol test condition min. max. unit note x8 x9 x18 x36 input leakage current i li ? 2 +2 a i/o leakage current i lo ? 2 +2 a operating supply current i dd v in v il or v in v ih , -e33 520 520 580 740 ma (read cycle / write cycle) i i/o = 0 ma,. cycle = max. -e40 460 460 520 650 standby supply current i sb1 v in v il or v in v ih , -e33 390 390 400 430 ma (nop) i i/o = 0 ma,. cycle = max. -e40 370 370 380 400 inputs static output high voltage v oh(low) |i oh | 0.1 ma v dd q ? 0.2 v dd q v 3, 4 v oh note1 v dd q/2 ? 0.12 v dd q/2+0.12 v 3, 4 output low voltage v ol(low) i ol 0.1 ma v ss 0.2 v 3, 4 v ol note2 v dd q/2 ? 0.12 v dd q/2+0.12 v 3, 4 notes 1. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 2. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 3. ac load current is higher than the shown dc values. 4. hstl outputs meet jedec hstl class i standards.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 18 of 38 nov 09, 2012 dc characteristics 2 (t a = -40 to 85 c, v dd = 1.8 0.1 v) parameter symbol test condition min. max. unit note x8 x9 x18 x36 input leakage current i li ? 2 +2 a i/o leakage current i lo ? 2 +2 a operating supply current i dd v in v il or v in v ih , -e33y 640 640 710 870 ma (read cycle / write cycle) i i/o = 0 ma,. cycle = max. -e40y 580 580 650 780 standby supply current i sb1 v in v il or v in v ih , -e33y 510 510 520 550 ma (nop) i i/o = 0 ma,. cycle = max. -e40y 490 490 500 520 inputs static output high voltage v oh(low) |i oh | 0.1 ma v dd q ? 0.2 v dd q v 3, 4 v oh note1 v dd q/2 ? 0.12 v dd q/2+0.12 v 3, 4 output low voltage v ol(low) i ol 0.1 ma v ss 0.2 v 3, 4 v ol note2 v dd q/2 ? 0.12 v dd q/2+0.12 v 3, 4 notes 1. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 2. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) 15% for values of 175 rq 350 . 3. ac load current is higher than the shown dc values. 4. hstl outputs meet jedec hstl class i standards.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 19 of 38 nov 09, 2012 capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. max. unit input capacitance (address, c ontrol) cin vin = 0 v 5 pf input / output capacitance ci/o vi/o = 0 v 7 pf (d, q, cq, cq#) clock input capacitance cclk vclk = 0 v 6 pf remark these parameters are periodically sampled and not 100% tested. thermal characteristics parameter symbol substrate airflow typ. unit thermal resistance ja 4-layer 0 m/s 16.5 c/w from junction to ambient air 1 m/s 13.2 c/w 8-layer 0 m/s 15.5 c/w 1 m/s 12.6 c/w thermal characterization parameter jt 4-layer 0 m/s 0.07 c/w from junction to the top center 1 m/s 0.13 c/w of the package surface 8-layer 0 m/s 0.06 c/w 1 m/s 0.12 c/w thermal resistance jc 3.86 c/w from junction to case
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 20 of 38 nov 09, 2012 ac characteristics (t a = 0 to 70 c, t a = ? 40 to 85 c,v dd = 1.8 0.1 v) ac test conditions (v dd = 1.8 0.1 v, v dd q = 1.4 v to v dd ) input waveform (rise / fall time 0.3 ns) 0.75 v 0.75 v test points 1.25 v 0.25 v output waveform v dd q / 2 v dd q / 2 test points output load condition figure 1. external load at test v dd q / 2 0.75 v 50 z o = 50 250 sram v ref zq
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 21 of 38 nov 09, 2012 read and write cycle parameter symbol -e33,-e33y -e40,-e40y unit note (300 mhz) (250 mhz) min. max. min. max. clock average clock cycle time tkhkh 3.3 8.4 4.0 8.4 ns 1 (k, k#, c, c#) clock phase jitter (k, k#, c, c#) tkc var 0.2 0.2 ns 2 clock high time (k, k#, c, c#) tkhkl 1.32 1.6 ns clock low time (k, k#, c, c#) tklkh 1.32 1.6 ns clock high to clock# high tkhk#h 1.49 1.8 ns (k k#, c c#) clock# high to clock high tk#hkh 1.49 1.8 ns (k# k, c# c) clock to data clock tkhch 0 1.45 0 1.8 ns (k c, k# c#) pll lock time (k, c) tkc lock 20 20 cq#) cq# high to cq high tcq#hcqh 1.24 1.55 ns 5 (cq# cq) c, c# high to output valid tchqv 0.45 0.45 ns c, c# high to output hold tchqx ?0.45 ?0.45 ns c, c# high to echo clock valid tchcqv 0.45 0.45 ns c, c# high to echo clock hold tchcqx ?0.45 ?0.45 ns cq, cq# high to output valid tcqhqv 0.27 0.3 ns 6 cq, cq# high to output hold tcqhqx ?0.27 ?0.3 ns 6 c high to output high-z tchqz 0.45 0.45 ns c high to output low-z tchqx1 ?0.45 ?0.45 ns setup times address valid to k rising e dge tavkh 0.4 0.5 ns 7 control inputs (r#, w#) valid to tivkh 0.4 0.5 ns 7 k rising edge data inputs and write data select tdvkh 0.3 0.35 ns 7 inputs (bwx#, nwx#) valid to k, k# rising edge hold times k rising edge to address hold tkhax 0.4 0.5 ns 7 k rising edge to control input s tkhix 0.4 0.5 ns 7 (r#, w#) hold k, k# rising edge to data inputs tkhdx 0.3 0.35 ns 7 and write data select inputs (bwx#, nwx#) hold
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 22 of 38 nov 09, 2012 notes 1. when debugging the system or board, these products can operate at a clock freque ncy slower than tkhkh (max.) without the pll circuit being used, if dll# = low. read latency (rl) is changed to 1.0 clock cycle in this operation. the ac/dc characteristics cannot be guaranteed, however. 2. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. tkc var (max.) indicates a peak-to-peak value. 3. v dd slew rate must be less than 0.1 v dc per 50 ns for pll lock retention. pll lock time begins once v dd and input clock are stable. it is recommended that the device is ke pt nop (r# = w# = high) during these cycles. 4. k input is monitored for this operation. see below for the timing. k k tkc reset or tkc reset 5. guaranteed by design. 6. echo clock is very tightly controlled to data valid / data hold. by design, there is a 0.1 ns variation from echo clock to data. the data sheet parameters reflect tester guardbands and test setup variations. 7. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. remarks 1. this parameter is sampled. 2. test conditions as specified with the output loadin g as shown in ac test conditions unless otherwise noted. 3. control input signals may not be operated with pulse widths less than tkhkl (min.). 4. if c, c# are tied high, k, k# become the references for c, c# timing parameters. 5. v dd q is 1.5 v dc.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 23 of 38 nov 09, 2012 read and write timing k address data in k# 246 13 5 7 tkhk#h tk#hkh c c# tkhch nop read read tkhkl tklkh q00 q02 data out q01 q03 r# w# tkhkl tklkh tchqx1 tchqx tchqz d10 d12 d11 d13 tdvkh tkhdx tdvkh tkhdx tkhkh tivkh tkhix tavkh tkhax cq cq# tcqhqx tchqv tchcqx tchcqv tchcqx tchcqv write nop qx3 tchqx tchqv write tivkh tkhix a0 a1 a2 a3 d30 d32 d31 d33 q20 q22 q21 q23 qx2 tkhk#h tk#hkh tkhch tkhkh tcqhqv tcq#hcqh tcqhcq#h remarks 1. q00 refers to output from address a0+0. q01 refers to output from the next internal burst address following a0,i.e.,a0+1. 2. outputs are disabled (high impedance) 3.5 clock cycles after the last read (r# = low) is input in the sequences of [read]-[nop]-[nop], [read]-[write]-[nop] and [read]-[nop]-[write]. 3. in this example, if address a2 = a1, data q20 = d10, q21 = d11, q22 = d12 and q23 = d13. write data is forwarded immediately as read results.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 24 of 38 nov 09, 2012 application example sram controller data in data out address r# w# bw# sram#1 cq/cq# sram#4 cq/cq# source clk/clk# return clk/clk# zq q cq# cq sram#4 d a r# w# bwx# c/c# k/k# r r v t v t r v t r v t r v t r v t r = 250 r = 250 zq q cq# cq sram#1 d a r# w# bwx# c/c# k/k# r = 50 v t = v ref . . . . . . remark ac characteristics are defined at the condition of sram outputs, cq, cq# and q with termination.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 25 of 38 nov 09, 2012 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name pin assignments description tck 2r test clock input. all input are capt ured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the comm and input for the tap controller state machine. tdi 11r test data input. this is the input si de of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instru ction that is currently loaded in the tap instruction. tdo 1r test data output. this is the output si de of the serial registers placed between tdi and tdo. output changes in response to the falling edge of tck. remark the device does not have trst (tap reset). the test -logic reset state is entered while tms is held high for five rising edges of tck. the tap contro ller state is also reset on the sram power-up. jtag dc characteristics (t a = 0 to 70 c, v dd = 1.8 0.1 v, unless otherwise noted) parameter symbol conditions min. max. unit jtag input leakage current i li 0 v v in v dd ? 5.0 + 5.0 a jtag i/o leakage current i lo 0 v v in v dd q, ? 5.0 + 5.0 a outputs disabled jtag input high voltage v ih 1.3 v dd + 0.3 v jtag input low voltage v il ? 0.3 + 0.5 v jtag output high voltage v oh1 | i ohc | = 100 a 1.6 v v oh2 | i oht | = 2 ma 1.4 v jtag output low voltage v ol1 i olc = 100 a 0.2 v v ol2 i olt = 2 ma 0.4 v
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 26 of 38 nov 09, 2012 jtag ac test conditions input waveform (rise / fall time 1 ns) 0.9 v 0.9 v test points 1.8 v 0 v output waveform 0.9 v 0.9 v test points output load figure 2. external load at test tdo z o = 50 v tt = 0.9 v 20 pf 50
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 27 of 38 nov 09, 2012 jtag ac characteristics (t a = 0 to 70 c) parameter symbol conditions min. max. unit clock clock cycle time t thth 50 ns clock frequency f tf 20 mhz clock high time t thtl 20 ns clock low time t tlth 20 ns output time tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns setup time tms setup time t mvth 5 ns tdi valid to tck high t dvth 5 ns capture setup time t cs 5 ns hold time tms hold time t thmx 5 ns tck high to tdi invalid t thdx 5 ns capture hold time t ch 5 ns jtag timing diagram t thth t tlov t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo t tlox
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 28 of 38 nov 09, 2012 scan register definition (1) register name description instruction register the instruction register holds the instru ctions that are execut ed by the tap controller when it is moved into the run-test/idle or the various data register stat e. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at pow er-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed throug h the rams tap to another device in the scan chain with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture- dr state with the idcode command loaded in the instruction register. t he register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr st ate and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe whic h device bump connects to each boundary register location. the first column defines the bit?s position in the boundary register. the second column is the name of the input or i/o at the bum p and the third column is the bump number. scan register definition (2) register name bit size unit instruction register 3 bit bypass register 1 bit id register 32 bit boundary register 109 bit id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit pd46365084b 4m x 8 xxxx 0000 0000 0100 1101 00000010000 1 pd46365094b 4m x 9 xxxx 0000 0000 0 100 1110 00000010000 1 pd46365184b 2m x 18 xxxx 0000 0000 0100 1111 00000010000 1 pd46365364b 1m x 36 xxxx 0000 0000 0101 0000 00000010000 1
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 29 of 38 nov 09, 2012 scan exit order bit signal name bump bit signal name bump bit signal name bump no. x8 x9 x18 x36 id no. x8 x9 x18 x36 id no. x8 x9 x18 x36 id 1 c# 6r 37 nc nc nc d15 10d 73 nc nc nc q28 2c 2 c 6p 38 nc nc nc q15 9e 74 q4 q5 q11 q20 3e 3 a 6n 39 nc nc q7 q7 10c 75 d4 d5 d11 d20 2d 4 a 7p 40 nc nc d7 d7 11d 76 nc nc nc d29 2e 5 a 7n 41 nc nc nc d16 9c 77 nc nc nc q29 1e 6 a 7r 42 nc nc nc q16 9d 78 nc nc q12 q21 2f 7 a 8r 43 q3 q4 q8 q8 11b 79 nc nc d12 d21 3f 8 a 8p 44 d3 d4 d8 d8 11c 80 nc nc nc d30 1g 9 a 9r 45 nc nc nc d17 9b 81 nc nc nc q30 1f 10 nc q0 q0 q0 11p 46 nc nc nc q17 10b 82 q5 q6 q13 q22 3g 11 nc d0 d0 d0 10p 47 cq 11a 83 d5 d6 d13 d22 2g 12 nc nc nc d9 10n 48 a a vss vss 10a 84 dll# 1h 13 nc nc nc q9 9p 49 a 9a 85 nc nc nc d31 1j 14 nc nc q1 q1 10m 50 a 8b 86 nc nc nc q31 2j 15 nc nc d1 d1 11n 51 a 7c 87 nc nc q14 q23 3k 16 nc nc nc d10 9m 52 nc 6c 88 nc nc d14 d23 3j 17 nc nc nc q10 9n 53 r# 8a 89 nc nc nc d32 2k 18 q0 q1 q2 q2 11l 54 nc nc nc bw1# 7a 90 nc nc nc q32 1k 19 d0 d1 d2 d2 11m 55 nw0# bw0# bw0# bw0# 7b 91 q6 q7 q15 q24 2l 20 nc nc nc d11 9l 56 k 6b 92 d6 d7 d15 d24 3l 21 nc nc nc q11 10l 57 k# 6a 93 nc nc nc d33 1m 22 nc nc q3 q3 11k 58 nc nc nc bw3# 5b 94 nc nc nc q33 1l 23 nc nc d3 d3 10k 59 nw1# nc bw1# bw2# 5a 95 nc nc q16 q25 3n 24 nc nc nc d12 9j 60 w# 4a 96 nc nc d16 d25 3m 25 nc nc nc q12 9k 61 a 5c 97 nc nc nc d34 1n 26 q1 q2 q4 q4 10j 62 a 4b 98 nc nc nc q34 2m 27 d1 d2 d4 d4 11j 63 a a a nc 3a 99 q7 q8 q17 q26 3p 28 zq 11h 64 vss 2a 100 d7 d8 d17 d26 2n 29 nc nc nc d13 10g 65 cq# 1a 101 nc nc nc d35 2p 30 nc nc nc q13 9g 66 nc nc q9 q18 2b 102 nc nc nc q35 1p 31 nc nc q5 q5 11f 67 nc nc d9 d18 3b 103 a 3r 32 nc nc d5 d5 11g 68 nc nc nc d27 1c 104 a 4r 33 nc nc nc d14 9f 69 nc nc nc q27 1b 105 a 4p 34 nc nc nc q14 10f 70 nc nc q10 q19 3d 106 a 5p 35 q2 q3 q6 q6 11e 71 nc nc d10 d19 3c 107 a 5n 36 d2 d3 d6 d6 10e 72 nc nc nc d28 1d 108 a 5r 109 ? internal remarks bump id 10a of bit no. 48 can also be used as nc if the product is x18 or x36. bump id 2a of bit no. 64 can also be used as nc. the register always in dicates low, however.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 30 of 38 nov 09, 2012 jtag instructions instructions description extest the extest instruction allows circuitry external to the component package to be tested. boundary-scan register cells at output pins are used to apply test vectors, while those at input pins capture test result s. typically, the first test vector to be applied using the extest instruction will be shifted into t he boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output drive is turned on and the preload data is driven onto the output pins. idcode the idcode inst ruction causes the id rom to be lo aded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass when the bypass instruction is loaded in the in struction register, the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift- dr state. this allows the board level scan path to be shortened to fac ilitate testing of other devices in the scan path. sample / preload sample / preload is a standard 11 49.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and q pins into the boundary scan register. because the ram clo ck(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring cont ents while the input buffers are in transition (i.e., in a metastabl e state). although allowing the tap to sample metastable input will not harm the device, r epeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (tcs plus tch). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo p ins. sample-z if the sample-z instruction is loaded in the instruction register, all ram q pins are forced to an inactive drive state (high impedance) a nd the boundary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction coding ir2 ir1 ir0 instruction note 0 0 0 extest 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 reserved 2 1 0 0 sample / preload 1 0 1 reserved 2 1 1 0 reserved 2 1 1 1 bypass notes 1. tristate all q pins and capture the pad values into a serial scan latch. 2. do not use this instruction code because th e vendor uses it to evaluate this product.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 31 of 38 nov 09, 2012 output pin states of cq, cq# and q instructions control-register status output pin status cq,cq# q extest 0 update high-z 1 update update idcode 0 sram sram 1 sram sram sample-z 0 high-z high-z 1 high-z high-z sample 0 sram sram 1 sram sram bypass 0 sram sram 1 sram sram remark the output pin statuses during each instruction vary according to the control-register status (value of boundary scan register, bit no. 109). there are three statuses: update : contents of the ?update register? are output to the output pin (qdr pad). sram : contents of the sram internal output ?sram output? are output to the output pin (qdr pad). high-z : the output pin (qdr pad) becomes high impedance by controlling of the ?high-z jtag ctrl?. the control-register status is set during update-dr at the extest or sample instruction. sram capture register boundary scan register update register qdr pad sram output driver high-z jtag ctrl high-z update sram output
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 32 of 38 nov 09, 2012 boundary scan register status of output pins cq, cq# and q instructions sram status boundar y scan register status note cq,cq# q extest read (low-z) pad pad nop (high-z) pad pad idcode read (low-z) ? ? no definition nop (high-z) ? ? sample-z read (low-z) pad pad nop (high-z) pad pad sample read (low-z) in ternal internal nop (high-z) internal pad bypass read (low-z) ? ? no definition nop (high-z) ? ? remark the boundary scan register st atuses during execution each instruction vary according to th e instruction code and sram operation mode. there are two statuses: pad : contents of the output pin (qdr pad) are captured in the ?capture register? in the boundary scan register. internal : contents of the sram internal output ?sram output? are captured in the ?capture register? in the boundary scan register. pad internal sram output driver update register qdr pad high-z jtag ctrl capture register sram output boundary scan register
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 33 of 38 nov 09, 2012 tap controller state diagram test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11 disabling the test access port it is possible to use this device without utilizing the ta p. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms may be left open but fix them to v dd via a resistor of about 1 k when the tap controller is not used. tdo should be left unconnected also when the tap co ntroller is not used.
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 34 of 38 nov 09, 2012 test logic operation (instruction scan) tck controller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 35 of 38 nov 09, 2012 test logic (data scan) controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instruction register state idcode run-test/idle select-dr-scan select-ir-scan output inactive tck
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 36 of 38 nov 09, 2012 package dimensions item dimensions d e w a a1 a2 e 13.000.10 15.000.10 0.30 0.370.05 ? 0.05 0.10 1.350.11 0.98 1.00 (unit:mm) 0.15 0.25 1.50 0.50 s e y1 s a a1 a2 s y s x bab m s wa s wb ze zd index mark a b 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l m n p r e d x y y1 zd ze b 0.50 t165f1-100-eq1 +0.10 165-pin plastic bga(13x15)
pd46365084b, pd46365094b, pd46365184b, pd46365364b r10ds0090ej0400 rev.4.00 page 37 of 38 nov 09, 2012 recommended soldering condition please consult with our sales offices for soldering conditions of these products. types of surface mount devices pd46365084bf1-eq1 : 165-pin plastic bga (13 x 15) pd46365094bf1-eq1 : 165-pin plastic bga (13 x 15) pd46365184bf1-eq1 : 165-pin plastic bga (13 x 15) pd46365364bf1-eq1 : 165-pin plastic bga (13 x 15) quality grade ? a quality grade of the products is ?standard?. ? anti-radioactive design is not implemented in the products. ? semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the ground and so forth.
all trademarks and registered trademarks are t he property of their respective owners. c - 38 revision history pd46365084b, pd46365094b, pd46365184b, pd46365364b rev. date description page summary rev.1.00 ?11.05.19 - new data sheet rev.2.00 ?11.11.07 p11 modified comments for power on sequence rev.3.00 ?12.07.13 all addition : e**y series rev.4.00 ?12.11.09 all addition : -e33,-e33y series, lead series deletion : -e50,-e50y series
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